Honda Motor Co. and Renesas Electronics officially signed a cooperation agreement at CES 2025 today, announcing the joint development of a high-performance System-on-Chip (SoC) for Software-Defined Vehicles (SDVs). This chip, manufactured using TSMC’s 3nm process, will deliver 2000 TOPS of AI computing power and an energy efficiency ratio of 20 TOPS/W, and is scheduled to be installed in Honda’s “0 Series” all-electric models to be launched in the late 2020s.​ According to Honda’s R&D director, the chip is specifically designed for centralized electrical and electronic architectures, capable of integrating multi-domain functions such as Autonomous Driving (AD), power control, and intelligent cockpits, replacing traditional distributed ECU clusters. Its core advantage lies in the Chiplet combination solution, which integrates Renesas’ 5th-generation R-Car X5 chip infrastructure with Honda’s independently developed AI accelerator. This not only meets the computing power requirements for L4-level autonomous driving but also reduces the energy consumption burden of electric vehicles. A Renesas Electronics executive added that this customized chip solution ensures functional safety through Hardware Isolation Technology (FFI) and will enable performance iteration via upgrade modules in the future.​ Industry analysts point out that this collaboration marks Japanese automakers’ breakthrough in breaking the pattern of relying on external suppliers in the field of core intelligent cockpit hardware. With 2000 TOPS of computing power reaching the industry’s top level, it will narrow the gap with competitors such as Tesla and BYD in terms of autonomous driving chips.​